The high level of transparency of optical networks with regard to data transmission rates and the use of different transmission methods and transmission protocols for the transmission of digital information (for example, the Synchronous Digital Hierarchy SDH, Gigabit-Ethernet, Fiber Channel) requires future devices for data regeneration and for reproduction of the amplitude, flank and clock of a transmitted digital data signal or data stream—also referred to as “3R data regeneration”.
Apparatuses for producing a clock signal from a digital data stream or from a data signal stream are known. Phase/frequency control loops or phase locked loops are frequently used for clock recovery and include, for example, a phase discriminator, a frequency discriminator, a loop filter, voltage controlled oscillators (also referred to as VCOs) and variable digital frequency dividers. The function of phase locked loops for clock recovery from a digital data stream and for sampling of the digital data stream to be regenerated via a sampling flipflop are sufficiently well known to those skilled in the art, such that their method of operation will not be described in further detail.
Various methods for determining the data transmission rate of the digital data stream are used to preset the phase locked loop. All the methods used, in particular, in wide area networks or WAN communications networks are based on more or less exactly determining the statistically distributed flank changes in the data stream within a defined observation time period. Conclusions can be drawn on the actual data transmission rate from the number of flank changes identified. These methods are also referred to as flank density analyses. Apart from the described flank density analysis, period duration measurements of individual bits are also used for low transmission rates.
By way of example, Laid-Open Specification DE 197 04 299 A1 describes an apparatus for producing a clock signal from a data signal, and a bit rate identification device for determining the bit rate of the incoming data signal. The apparatus includes a phase/frequency control device and a frequency divider device which is arranged in the feedback part of the phase/frequency control device and can be switched via a data word. The switchable frequency divider device is connected to the bit rate identification device, to which the digital data stream and at least one reference frequency signal can be supplied. The bit rate identification device provides a bit-rate-dependent data word as a function of the applied reference frequency signal and the digital data stream passed to it. This is then supplied to the frequency divider device arranged in the phase/frequency control device. The described apparatus for producing a clock signal from a digital data signal or data stream has the disadvantage that the resolution of the identification circuit is highly limited; that is, digital data stream transmission rates which differ by less than a factor of 4 cannot be distinguished reliably in this way. A further disadvantage is the risk of false synchronization to side lines in the frequency spectrum during the transmission of certain data contents, for example, when transmitting AIS information in SDH signals (Synchronous Digital Hierarchy).
The present invention is, therefore, directed toward improving the production of a clock signal from a transmitted digital data signal during a synchronization process and, in particular, the synchronization of the clock signal to the incoming digital data signal.